IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems https://www.computer.org/csdl/journal/si Browse the leading transactions in cloud computing, machine intelligence, mobile computing, distributed systems, and dozens of other technologies. en-us https://s3.amazonaws.com/ieeecs.cdn.common/images/computer.org/CSLogo_dark.png IEEE Computer Society Digital Library List of 100 recently published journal articles. https://www.computer.org/csdl A Self-Feeding-Priority SECE for Piezoelectric Energy Harvesting From Diverse Kinetic Energy https://www.computer.org/csdl/journal/si/2026/08/11510484/2ggU0I4kwTe 07/29/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687854 High-Performance FPGA-Based LZ77 Accelerator Design With Deep-Search Capability https://www.computer.org/csdl/journal/si/2026/08/11513002/2gkdYAUaFtC 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689072 Low-Area and High-Speed 10-Transistor/Bit Incrementers and Decrementers With Group-Carry Generation https://www.computer.org/csdl/journal/si/2026/08/11514894/2gpcBlhWWWI 07/29/2026 11:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687943 Low-Complexity Parallel Syndrome Computation and Chien Search Architecture Based on Reed--Muller Transform https://www.computer.org/csdl/journal/si/2026/08/11514895/2gpcBsCGlk4 07/29/2026 11:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689292 Analysis and Validation of Duty-Cycle-Based MPPT for Piezoelectric Energy Harvesting: Impact of Nonideal Losses on Optimal Duty Cycle https://www.computer.org/csdl/journal/si/2026/08/11516484/2gqRrrMNoOI 07/29/2026 11:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689112 FPUltra: An Area-Efficient Single-Precision Floating-Point Unit for Cost-Sensitive RISC-V Cores https://www.computer.org/csdl/journal/si/2026/08/11516488/2gqRrP7jfFu 07/29/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690450 An Energy-Efficient Block-Convolution-Based Super-Resolution Processor With Tiling Artifact Reduction https://www.computer.org/csdl/journal/si/2026/08/11516490/2gqRrDdibtK 07/29/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690901 Reconfigurable In-Memory Computing With Compute-Fusion SAR ADC for Area-Efficient Pipelined MAC Operations https://www.computer.org/csdl/journal/si/2026/08/11516499/2gqRrfj0SeQ 07/29/2026 11:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689104 Efficient NoC for Embedded Heterogeneous Multi-Core DSPs https://www.computer.org/csdl/journal/si/2026/08/11517445/2gswp05S58s 07/29/2026 11:02 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690726 Identifying Failing Flip-Flops in Scan-Based Designs Using Highly Compressed Test Results https://www.computer.org/csdl/journal/si/2026/08/11520190/2gtPS9Y6XzG 07/29/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3691865 A Hardware-Efficient Reed--Solomon Decoding Architecture for Single-Symbol Error Correcting in High-Bandwidth Memory https://www.computer.org/csdl/journal/si/2026/08/11520913/2gvQ8Mf4v2U 07/29/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692208 MoS<sub>2</sub>-Enhanced Antisymmetric 2T2R Logic Unit for One-Step Write/Compute In-Memory XNOR in BNN Accelerators https://www.computer.org/csdl/journal/si/2026/08/11520918/2gvQ8AUxi7e 07/29/2026 11:05 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3691526 A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay https://www.computer.org/csdl/journal/si/2026/08/11523195/2gCuDrr4APC 07/29/2026 11:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690678 A Multibit ΔΣ TDC With Space--Time Averaging for UWB Transceivers Achieving ToF-Based Fine Ranging https://www.computer.org/csdl/journal/si/2026/08/11524206/2gCuDzirRao 07/29/2026 11:05 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692273 Processing-in-Memory Architecture for In-Storage Information Retrieval on 3-D NAND Flash Solid-State Drives https://www.computer.org/csdl/journal/si/2026/08/11524212/2gCuDHSXlbq 07/29/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692428 TQ-SPUF: A Software PUF Design Based on HEVC Transform and Quantization Module for Device Security and Video Anti-Tampering https://www.computer.org/csdl/journal/si/2026/08/11526825/2gCuDkx1uGk 07/29/2026 11:01 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690749 Average-6.5T Near-Threshold Twin Cell With Shared Read Assist for IoT Applications https://www.computer.org/csdl/journal/si/2026/08/11534129/2gHspZ1Mg6s 07/29/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693724 Fused-STA: Automated Design Space Exploration of a Fused Systolic Tensor Array for Universal Deep Learning Acceleration https://www.computer.org/csdl/journal/si/2026/08/11535523/2gO695OSi6Q 07/29/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693713 RMC PUF: A Highly Reliable PUF Architecture Based on Recursive Markov Chain Obfuscation https://www.computer.org/csdl/journal/si/2026/08/11535587/2gO69ff2LNC 07/29/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693479 Right-Sized Security: Configurable Security Engine for Supply-Chain Integrity in Resource-Constrained System-on-Chip Designs https://www.computer.org/csdl/journal/si/2026/08/11535588/2gO69oNJdok 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693611 A Novel Unified Newton Structure-Based Fractional Delay Filter for Low-Complexity Reconfigurable Arbitrary Bandwidth Filters https://www.computer.org/csdl/journal/si/2026/08/11535590/2gO68WTVGJa 07/29/2026 11:02 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693050 System-Level Fault-Tolerant Reconfiguration of 3-D VLSI Processor Arrays Under Multicomponent Failures https://www.computer.org/csdl/journal/si/2026/08/11536087/2gPLbnjB9a8 07/29/2026 11:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3695877 HardVault: A Hybrid FPGA-Based Ethereum-Bitcoin Cold Wallet https://www.computer.org/csdl/journal/si/2026/08/11540335/2gY3O45Vlja 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3696577 A 7.33 nW Ratio Wake-Up Timer With XO and Auxiliary Oscillator for Real-Time Shock Recovery https://www.computer.org/csdl/journal/si/2026/08/11543517/2gZIEDxzsD6 07/29/2026 11:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3695454 Balancing FP8 Computation Accuracy and Efficiency on Digital CIM via Shift-Aware On-the-Fly Aligned-Mantissa Bitwidth Prediction https://www.computer.org/csdl/journal/si/2026/08/11543519/2gZIEP9HNCM 07/29/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693970 Toward Efficient Edge AI With Heterogeneous Computing and Multilevel Optimization https://www.computer.org/csdl/journal/si/2026/08/11548615/2h32c6n8k12 07/29/2026 11:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3697086 A Memory-Optimized Constant Geometry NTT-Based Polynomial Multiplier With a Conflict-Free Bit-Reverse Reordering Method https://www.computer.org/csdl/journal/si/2026/08/11551517/2h32ccJGKOI 07/29/2026 11:05 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693877 Design of Random Forest-Based Low-Power VLSI Architecture to Detect Congestive Heart Failure for Wearable Devices https://www.computer.org/csdl/journal/si/2026/08/11551523/2h32c1CuH04 07/29/2026 11:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3697012 Polar Code With Parity Check-Assisted Pruning for Error Correction in Modern Flash Memory https://www.computer.org/csdl/journal/si/2026/08/11552366/2h4HZwdVfRC 07/29/2026 11:00 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689019 An Efficient Hardware Accelerator for CKKS En/Decoding and En/Decryption With Dynamic Twiddle Factor Generation https://www.computer.org/csdl/journal/si/2026/08/11553463/2h9GAM4t8iI 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3695913 Neuromorphic Hyperdimensional Computing for Efficiently Processing Event-Based Data https://www.computer.org/csdl/journal/si/2026/08/11558557/2heEFWBRtEQ 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3695182 Rethinking Area Optimization for High-Throughput Hardware Accelerator of Number Theoretic Transform: A Case Study on ML-KEM https://www.computer.org/csdl/journal/si/2026/08/11558559/2heEG2vsPbW 07/30/2026 8:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3697390 QSNNA: An Energy-Efficient Quaternary Spiking Neural Network Accelerator for Seizure Detection https://www.computer.org/csdl/journal/si/2026/08/11563477/2hli83Sb2X6 07/29/2026 11:01 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3696357 A High-Efficiency Optimization Design Method for ADC System Under Multiple PVT Conditions via Transfer Learning https://www.computer.org/csdl/journal/si/2026/08/11563592/2hli8aEyYAE 07/29/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692184 A 71.3 dB-SNDR Fully Passive Speed Enhanced 4× OSR Second-Order NS SAR ADC With Excessive-Capacitor-Reset Switching Scheme https://www.computer.org/csdl/journal/si/2026/08/11574516/2hwUtcd00uI 07/29/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686072 ENLIVEN: End-to-End NPU--ISP Codesign for Low-Latency and Hardware-Optimized Visual Processing https://www.computer.org/csdl/journal/si/2026/08/11577180/2hAerQvxExW 07/29/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3694263 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information https://www.computer.org/csdl/journal/si/2026/08/11626105/2isEKSNZgsg 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3708948 Table of Contents https://www.computer.org/csdl/journal/si/2026/08/11626106/2isEIQcTfGg 07/29/2026 11:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3708950 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information https://www.computer.org/csdl/journal/si/2026/08/11626107/2isEKEG193a 07/29/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3708946 A Real-Time End-to-End Event-Based Tactile Sensing System https://www.computer.org/csdl/journal/si/2026/07/11398397/2edaMUaV1Wo 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3663124 A 55 MHz Bandwidth and Sub-<italic>μ</italic>V Offset Precision Amplifier With Two-Step Dynamic Offset Calibration and Noise Suppression Techniques https://www.computer.org/csdl/journal/si/2026/07/11421097/2eAppYNEWkM 07/03/2026 8:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3668196 A Structured-Sparsity-Based Design Approach for Energy-Efficient Spiking Transformer Processing https://www.computer.org/csdl/journal/si/2026/07/11455960/2f9c3LODyrC 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3675299 Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits https://www.computer.org/csdl/journal/si/2026/07/11478736/2fzpoH9wS1W 07/02/2026 11:17 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3680902 ZACHO: Zero-Shot Agile Circuit Hardening Optimizer via Deep Reinforcement Learning https://www.computer.org/csdl/journal/si/2026/07/11481000/2fGocaEaEms 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3681140 Real-Time Proximity Sensing for Autonomous Systems: Custom AFE and FPGA Acceleration for FMCW Architecture https://www.computer.org/csdl/journal/si/2026/07/11481003/2fGoc3Hza2A 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3681565 A High-Precision Reference-Free Relaxation Oscillator With Supply-Tracking Switching Threshold https://www.computer.org/csdl/journal/si/2026/07/11481008/2fGobXyDtu0 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3682877 Hardware-Efficient Low-Distortion Sinusoidal Signal Generator Using FPGA-Based Dual-DAC Digital Predistortion https://www.computer.org/csdl/journal/si/2026/07/11487939/2g8jSGVsVb2 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3683742 A Fast-Locking Phase-Locked Loop With Joint Phase and Frequency Compensation Technique https://www.computer.org/csdl/journal/si/2026/07/11489523/2fTjQwT725a 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684335 HammerBlade in Silicon: A 12-nm 2048-Core RISC-V Manycore SoC With Ruche Networks https://www.computer.org/csdl/journal/si/2026/07/11494369/2fWDJpNfVg4 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684311 Design of High-Speed Multimodulus Divider With Fast EOC Generation Counters and High-Speed Reset Configuration https://www.computer.org/csdl/journal/si/2026/07/11495289/2g1CpiAQjgQ 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684891 Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks https://www.computer.org/csdl/journal/si/2026/07/11495290/2g1Cpww2tP2 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686238 Stealing AI Model Weights Through Covert Communication Channels https://www.computer.org/csdl/journal/si/2026/07/11495291/2g1CpHdGDVS 08/05/2026 3:02 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684645 Memory-Optimized Block Compression for High-Speed Memory Testing https://www.computer.org/csdl/journal/si/2026/07/11495467/2g3CViNmQIE 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686478 A Current-Steering DAC With a Complementary Structured Charge-Pump-Based Voltage-Limited Driver for Code-Dependent Error Suppression https://www.computer.org/csdl/journal/si/2026/07/11498708/2g6WFJ5FMeQ 07/02/2026 11:19 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3685243 A Single-Input Dual-Output Wireless Power Transfer System With Load-Optimized Matching Network https://www.computer.org/csdl/journal/si/2026/07/11499438/2g6WFoOun96 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686340 Prototyping JSCC on FPGA: A Swin Transformer Accelerator Toward High-Effciency Semantic Communications https://www.computer.org/csdl/journal/si/2026/07/11500572/2g6WFCCiYjC 07/06/2026 8:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3683054 A 2 nA, −70 dB at 1 MHz PSRR and Trimming-Less Dual-Output CMOS Voltage Reference With Pre-Stabilization for IoT Applications https://www.computer.org/csdl/journal/si/2026/07/11502012/2g6WFvH7tE4 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687231 A Fully Synthesizable 12-bit Event-Driven TDC-Assisted Two-Step Counter for Imagers Achieving 0.49-LSB INL in 28-nm CMOS https://www.computer.org/csdl/journal/si/2026/07/11503436/2gdlk5rZi0g 07/07/2026 8:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687014 A Booth-Based Digital Compute-in-Memory Macro With Bitwise-Efficient Multiphase Accumulation https://www.computer.org/csdl/journal/si/2026/07/11503459/2gdAlYYpN6g 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687178 Algorithm--Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity https://www.computer.org/csdl/journal/si/2026/07/11506321/2ggMy22g8x2 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686720 Energy-Efficient Logarithmic Floating-Point Multipliers Using Truncation-Based Error Compensation for Fault-Tolerant Applications https://www.computer.org/csdl/journal/si/2026/07/11506325/2ggMyeGgdNe 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689058 TriCIM: A General CIM-Capacity-Aware Framework for Optimizing Model, Layer, and Tile-Stationary Dataflows in CIM Accelerators https://www.computer.org/csdl/journal/si/2026/07/11511842/2gizpvGxs0o 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688907 A Bit-Level Loosely Coupled Spiking Neural Network Accelerator With Fast Inference and Hybrid Early Termination https://www.computer.org/csdl/journal/si/2026/07/11511848/2gizpiovVp6 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688394 Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning https://www.computer.org/csdl/journal/si/2026/07/11511852/2gizpCq5oli 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690001 A Groupwise Add--Multiply--Shift--Accumulate Datapath for Efficient DNN Accelerators https://www.computer.org/csdl/journal/si/2026/07/11513005/2gkdYIzUntK 07/02/2026 11:17 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689624 A Low-Power, High-Throughput Multimode FFT Processor Incorporating the ASPC Algorithm https://www.computer.org/csdl/journal/si/2026/07/11513678/2gkdZ0VSfWo 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688149 RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory https://www.computer.org/csdl/journal/si/2026/07/11513844/2gpcBLzgtz2 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687257 A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed--Solomon Decoder https://www.computer.org/csdl/journal/si/2026/07/11513845/2gpcBRLBlGo 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689157 Table of Contents https://www.computer.org/csdl/journal/si/2026/07/11589496/2hKbGs2HqhO 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700293 Guest Editorial: Special Section on the Asia Pacific Conference on Circuits and Systems—APCCAS 2025 https://www.computer.org/csdl/journal/si/2026/07/11589499/2hKbGX6DLPy 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693816 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information https://www.computer.org/csdl/journal/si/2026/07/11589511/2hKbJqv7YVa 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700289 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information https://www.computer.org/csdl/journal/si/2026/07/11589512/2hKbGHcfGPm 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700291 RLRM: Reinforcement Learning-Based Routing for Ring-Augmented Mesh NoC https://www.computer.org/csdl/journal/si/2026/06/11409425/2en8ghB6LSM 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664149 Exploiting Hardware Nonidealities for Robust Low-Precision Ensembles on ACIM https://www.computer.org/csdl/journal/si/2026/06/11410513/2eoNe8fixgY 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3666118 A Revision of the Quality Metrics of Physical Unclonable Functions https://www.computer.org/csdl/journal/si/2026/06/11419356/2eyKHpeFRsI 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664178 DayPQ: Dynamic Layerwise Pruning and Quantization for LLM Inference Acceleration https://www.computer.org/csdl/journal/si/2026/06/11419640/2eyKHh9FQSQ 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3666193 A Data-Driven Approach to Online Fault Detection in RRAM-Based Neuromorphic Hardware Using Adversarial-Inspired Test https://www.computer.org/csdl/journal/si/2026/06/11419654/2eyKH8T2hYk 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3667040 A Compact Inverter-Based Neural Amplifier With Local and System Dual CMFB Loops Through Paralleled Pseudo Transconductors https://www.computer.org/csdl/journal/si/2026/06/11421810/2eC4bWXAxqw 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3667606 Algorithm and Architecture of a Channel-Correlation-Resistant Massive MIMO Detector Based on Expectation Propagation https://www.computer.org/csdl/journal/si/2026/06/11424008/2eDJrkcPq2Q 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3668770 Highly Reliable RRAM-Based Physical Unclonable Function With Auto-Write Technique https://www.computer.org/csdl/journal/si/2026/06/11429683/2eNCoCODnPy 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3670888 DyTopK: Accelerating Top-K SpMV on Embedded FPGAs via Dynamic Floating-Point Quantization https://www.computer.org/csdl/journal/si/2026/06/11437544/2eVUNY8Pqgg 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673262 A Multimode Built-In Self-Test Circuit for Sequential Cell Timing Characteristics Based on Digital-to-Time Converter https://www.computer.org/csdl/journal/si/2026/06/11441982/2eXelEV8HrW 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673338 Design of a 65-nm CMOS Neuromorphic Circuit for Sequential Alphanumeric Pattern Detection With Experimental Verification https://www.computer.org/csdl/journal/si/2026/06/11450074/2f5Sh85VhwQ 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3674147 High-Accuracy, Low-Utilization Multichannel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multidimensional Delay Array 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