IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems https://www.computer.org/csdl/journal/si Browse the leading transactions in cloud computing, machine intelligence, mobile computing, distributed systems, and dozens of other technologies. en-us https://s3.amazonaws.com/ieeecs.cdn.common/images/computer.org/CSLogo_dark.png IEEE Computer Society Digital Library List of 100 recently published journal articles. https://www.computer.org/csdl A Real-Time End-to-End Event-Based Tactile Sensing System https://www.computer.org/csdl/journal/si/2026/07/11398397/2edaMUaV1Wo 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3663124 A 55 MHz Bandwidth and Sub-<italic>μ</italic>V Offset Precision Amplifier With Two-Step Dynamic Offset Calibration and Noise Suppression Techniques https://www.computer.org/csdl/journal/si/2026/07/11421097/2eAppYNEWkM 07/03/2026 8:03 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3668196 A Structured-Sparsity-Based Design Approach for Energy-Efficient Spiking Transformer Processing https://www.computer.org/csdl/journal/si/2026/07/11455960/2f9c3LODyrC 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3675299 Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits https://www.computer.org/csdl/journal/si/2026/07/11478736/2fzpoH9wS1W 07/02/2026 11:17 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3680902 ZACHO: Zero-Shot Agile Circuit Hardening Optimizer via Deep Reinforcement Learning https://www.computer.org/csdl/journal/si/2026/07/11481000/2fGocaEaEms 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3681140 Real-Time Proximity Sensing for Autonomous Systems: Custom AFE and FPGA Acceleration for FMCW Architecture https://www.computer.org/csdl/journal/si/2026/07/11481003/2fGoc3Hza2A 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3681565 A High-Precision Reference-Free Relaxation Oscillator With Supply-Tracking Switching Threshold https://www.computer.org/csdl/journal/si/2026/07/11481008/2fGobXyDtu0 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3682877 Hardware-Efficient Low-Distortion Sinusoidal Signal Generator Using FPGA-Based Dual-DAC Digital Predistortion https://www.computer.org/csdl/journal/si/2026/07/11487939/2g8jSGVsVb2 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3683742 A Fast-Locking Phase-Locked Loop With Joint Phase and Frequency Compensation Technique https://www.computer.org/csdl/journal/si/2026/07/11489523/2fTjQwT725a 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684335 HammerBlade in Silicon: A 12-nm 2048-Core RISC-V Manycore SoC With Ruche Networks https://www.computer.org/csdl/journal/si/2026/07/11494369/2fWDJpNfVg4 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684311 Design of High-Speed Multimodulus Divider With Fast EOC Generation Counters and High-Speed Reset Configuration https://www.computer.org/csdl/journal/si/2026/07/11495289/2g1CpiAQjgQ 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684891 Design of an Approximate Recursive Multiplier Based on Probability-Driven Intercolumn Error Cancellation and Its Application in Deep Neural Networks https://www.computer.org/csdl/journal/si/2026/07/11495290/2g1Cpww2tP2 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686238 Stealing AI Model Weights Through Covert Communication Channels https://www.computer.org/csdl/journal/si/2026/07/11495291/2g1CpHdGDVS 07/02/2026 11:19 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3684645 Memory-Optimized Block Compression for High-Speed Memory Testing https://www.computer.org/csdl/journal/si/2026/07/11495467/2g3CViNmQIE 07/02/2026 11:16 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686478 A Current-Steering DAC With a Complementary Structured Charge-Pump-Based Voltage-Limited Driver for Code-Dependent Error Suppression https://www.computer.org/csdl/journal/si/2026/07/11498708/2g6WFJ5FMeQ 07/02/2026 11:19 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3685243 A Single-Input Dual-Output Wireless Power Transfer System With Load-Optimized Matching Network https://www.computer.org/csdl/journal/si/2026/07/11499438/2g6WFoOun96 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686340 Prototyping JSCC on FPGA: A Swin Transformer Accelerator Toward High-Effciency Semantic Communications https://www.computer.org/csdl/journal/si/2026/07/11500572/2g6WFCCiYjC 07/06/2026 8:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3683054 A 2 nA, −70 dB at 1 MHz PSRR and Trimming-Less Dual-Output CMOS Voltage Reference With Pre-Stabilization for IoT Applications https://www.computer.org/csdl/journal/si/2026/07/11502012/2g6WFvH7tE4 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687231 A Fully Synthesizable 12-bit Event-Driven TDC-Assisted Two-Step Counter for Imagers Achieving 0.49-LSB INL in 28-nm CMOS https://www.computer.org/csdl/journal/si/2026/07/11503436/2gdlk5rZi0g 07/07/2026 8:04 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687014 A Booth-Based Digital Compute-in-Memory Macro With Bitwise-Efficient Multiphase Accumulation https://www.computer.org/csdl/journal/si/2026/07/11503459/2gdAlYYpN6g 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687178 Algorithm--Hardware Co-Design of Digital Compute-in-Memory Architecture Supporting Flexible and Temporal N:M Sparsity https://www.computer.org/csdl/journal/si/2026/07/11506321/2ggMy22g8x2 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3686720 Energy-Efficient Logarithmic Floating-Point Multipliers Using Truncation-Based Error Compensation for Fault-Tolerant Applications https://www.computer.org/csdl/journal/si/2026/07/11506325/2ggMyeGgdNe 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689058 TriCIM: A General CIM-Capacity-Aware Framework for Optimizing Model, Layer, and Tile-Stationary Dataflows in CIM Accelerators https://www.computer.org/csdl/journal/si/2026/07/11511842/2gizpvGxs0o 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688907 A Bit-Level Loosely Coupled Spiking Neural Network Accelerator With Fast Inference and Hybrid Early Termination https://www.computer.org/csdl/journal/si/2026/07/11511848/2gizpiovVp6 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688394 Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning https://www.computer.org/csdl/journal/si/2026/07/11511852/2gizpCq5oli 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3690001 A Groupwise Add--Multiply--Shift--Accumulate Datapath for Efficient DNN Accelerators https://www.computer.org/csdl/journal/si/2026/07/11513005/2gkdYIzUntK 07/02/2026 11:17 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689624 A Low-Power, High-Throughput Multimode FFT Processor Incorporating the ASPC Algorithm https://www.computer.org/csdl/journal/si/2026/07/11513678/2gkdZ0VSfWo 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3688149 RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory https://www.computer.org/csdl/journal/si/2026/07/11513844/2gpcBLzgtz2 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3687257 A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed--Solomon Decoder https://www.computer.org/csdl/journal/si/2026/07/11513845/2gpcBRLBlGo 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3689157 Table of Contents https://www.computer.org/csdl/journal/si/2026/07/11589496/2hKbGs2HqhO 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700293 Guest Editorial: Special Section on the Asia Pacific Conference on Circuits and Systems—APCCAS 2025 https://www.computer.org/csdl/journal/si/2026/07/11589499/2hKbGX6DLPy 07/02/2026 11:15 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3693816 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information https://www.computer.org/csdl/journal/si/2026/07/11589511/2hKbJqv7YVa 07/02/2026 11:18 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700289 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information https://www.computer.org/csdl/journal/si/2026/07/11589512/2hKbGHcfGPm 07/02/2026 11:14 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3700291 RLRM: Reinforcement Learning-Based Routing for Ring-Augmented Mesh NoC https://www.computer.org/csdl/journal/si/2026/06/11409425/2en8ghB6LSM 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664149 Exploiting Hardware Nonidealities for Robust Low-Precision Ensembles on ACIM https://www.computer.org/csdl/journal/si/2026/06/11410513/2eoNe8fixgY 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3666118 A Revision of the Quality Metrics of Physical Unclonable Functions https://www.computer.org/csdl/journal/si/2026/06/11419356/2eyKHpeFRsI 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664178 DayPQ: Dynamic Layerwise Pruning and Quantization for LLM Inference Acceleration https://www.computer.org/csdl/journal/si/2026/06/11419640/2eyKHh9FQSQ 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3666193 A Data-Driven Approach to Online Fault Detection in RRAM-Based Neuromorphic Hardware Using Adversarial-Inspired Test https://www.computer.org/csdl/journal/si/2026/06/11419654/2eyKH8T2hYk 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3667040 A Compact Inverter-Based Neural Amplifier With Local and System Dual CMFB Loops Through Paralleled Pseudo Transconductors https://www.computer.org/csdl/journal/si/2026/06/11421810/2eC4bWXAxqw 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3667606 Algorithm and Architecture of a Channel-Correlation-Resistant Massive MIMO Detector Based on Expectation Propagation https://www.computer.org/csdl/journal/si/2026/06/11424008/2eDJrkcPq2Q 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3668770 Highly Reliable RRAM-Based Physical Unclonable Function With Auto-Write Technique https://www.computer.org/csdl/journal/si/2026/06/11429683/2eNCoCODnPy 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3670888 DyTopK: Accelerating Top-K SpMV on Embedded FPGAs via Dynamic Floating-Point Quantization https://www.computer.org/csdl/journal/si/2026/06/11437544/2eVUNY8Pqgg 07/02/2026 11:13 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673262 A Multimode Built-In Self-Test Circuit for Sequential Cell Timing Characteristics Based on Digital-to-Time Converter https://www.computer.org/csdl/journal/si/2026/06/11441982/2eXelEV8HrW 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673338 Design of a 65-nm CMOS Neuromorphic Circuit for Sequential Alphanumeric Pattern Detection With Experimental Verification https://www.computer.org/csdl/journal/si/2026/06/11450074/2f5Sh85VhwQ 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3674147 High-Accuracy, Low-Utilization Multichannel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multidimensional Delay Array https://www.computer.org/csdl/journal/si/2026/06/11455386/2f7x7IExVss 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3676373 Thermal Insights of 3-D BS-PDN in Cloud Server SoC Using TCAD Modeling https://www.computer.org/csdl/journal/si/2026/06/11457484/2fhuysxvXck 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673227 A 0.2%-THD Sinusoidal Signal Generator With First-Order Analog Interpolation Over More Than Three Frequency Decades for EIS Applications https://www.computer.org/csdl/journal/si/2026/06/11457804/2fhuylKQqqI 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677049 A High-Performance ML-KEM Architecture With Task-Level Parallelism https://www.computer.org/csdl/journal/si/2026/06/11458095/2fj9IfeNO5a 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677808 Venusian: Rapid Wireless Baseband Validation via High-Level Programming and FPGA-Based RISC-V Accelerator Co-Design https://www.computer.org/csdl/journal/si/2026/06/11458096/2fj9Iujfihy 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677067 A Cryo-CMOS 4–5.9-GHz Fractional-N Cascaded PLL Achieving 36.9-fsrms Integrated Jitter and −69.1-dBc Fractional Spur https://www.computer.org/csdl/journal/si/2026/06/11458098/2fj9ICpFivK 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677458 ParaPM: Efficient Hardware Accelerator for Postquantum Signature With High-Performance Polynomial Multiplier https://www.computer.org/csdl/journal/si/2026/06/11458629/2fj9IljtvGM 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3678026 Hardware Acceleration of Kolmogorov–Arnold Network (KAN) in Large-Scale Systems https://www.computer.org/csdl/journal/si/2026/06/11466333/2fkOxwuLGb6 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3673356 A 65-nm 3T2R ReRAM Computing-in-Memory Macro Using a 4-bit 1-GS/s Two-Stage Pipelined 2-bit Output Comparator With a Successive Approximation-Like Architecture https://www.computer.org/csdl/journal/si/2026/06/11466337/2fkOxhSZG7e 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3676995 A 54.1–387.5-<italic>μ</italic>W 65-nm Multimodal SoC Integrating a Custom CISC Core for Edge IoT Applications https://www.computer.org/csdl/journal/si/2026/06/11471281/2fmtAjTWFQ4 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3670378 Model–Hardware Co-Design of Depthwise Separable Convolution With Interlayer Pipelining for Stereo Matching https://www.computer.org/csdl/journal/si/2026/06/11474801/2fuMiJkmiOI 07/02/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3678459 A Fast Injection and Low-Overhead Compensation Method for IR-Drop in RRAM-Based CNN In-Memory Computing https://www.computer.org/csdl/journal/si/2026/06/11475641/2fuMjrSOwGA 07/02/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677368 HiRe: A Hierarchical Reconfigurable Architecture for Large-Scale Multichiplet DNN Accelerators https://www.computer.org/csdl/journal/si/2026/06/11475665/2fuMiPPqHwk 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3676552 ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine https://www.computer.org/csdl/journal/si/2026/06/11476995/2fwqSevIIVO 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3680055 Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements https://www.computer.org/csdl/journal/si/2026/06/11477130/2fwqRUJbZT2 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3678304 Glitch-Aware Optimization of 4-2 Compressor-Based Approximate Multipliers https://www.computer.org/csdl/journal/si/2026/06/11480998/2fGochFjILm 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3682042 A Generalized Design Methodology for Multi-Input Collaborative-Flip Synchronized Switch Harvesting on Capacitors: From Theory to Optimization Strategy https://www.computer.org/csdl/journal/si/2026/06/11482690/2fJHZusCXao 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3680100 Finetune Chiplet Design Floorplan via KuanNet https://www.computer.org/csdl/journal/si/2026/06/11489524/2fTjQCQYmze 07/02/2026 11:08 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3681746 Overflow-Driven Dynamic Precision Scaling Fixed-Point Multiply-Accumulator Unit https://www.computer.org/csdl/journal/si/2026/06/11494365/2fWDJx9YvxS 07/02/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3680254 A Fast Convergence Background Calibration Technique for Gain Nonlinearity in Pipeline ADCs https://www.computer.org/csdl/journal/si/2026/06/11498514/2g3CVs5AyLC 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3678216 FANE: FPGA-Based FP8 Approximate Neural Network Engine https://www.computer.org/csdl/journal/si/2026/06/11503218/2gdAlKv9KWk 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3677683 Table of Contents https://www.computer.org/csdl/journal/si/2026/06/11547312/2gZIDIX9oVG 07/02/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692262 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information https://www.computer.org/csdl/journal/si/2026/06/11547351/2gZIAvddO6Y 07/02/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692260 IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information https://www.computer.org/csdl/journal/si/2026/06/11547352/2gZIC3ebm00 07/02/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3692258 VLSI Architecture for an Adaptive Transmission Estimation-Based Video Dehazing Method https://www.computer.org/csdl/journal/si/2026/05/11398398/2edaMOj1hbG 05/31/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3661796 A 28-nm 16-Kb SRAM Computing-in-Memory Macro With Dual Bitline Computing for Boolean Logic Operation and BWN MAC Operation https://www.computer.org/csdl/journal/si/2026/05/11405434/2elthKEGCSA 06/01/2026 8:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3662417 TRO-Based Dual-Domain Voltage Co-Regulation of Digital Logic and SRAM in SoCs https://www.computer.org/csdl/journal/si/2026/05/11405435/2elthRj7MSk 06/01/2026 8:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3663605 Efficient FPGA Acceleration for 4-bit CNNs via Quantization-Induced Structured Sparsity and LUT-Based Multiplication https://www.computer.org/csdl/journal/si/2026/05/11407484/2elthE9TPj2 05/31/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3663320 A Cryogenic 2T GC-eDRAM With an Inverter-Based Readout Scheme and an 80 ms Retention Time https://www.computer.org/csdl/journal/si/2026/05/11408928/2en8gqb33DG 05/31/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3661652 A Hardware-Efficient QR Algorithm and Its VLSI Architecture for Eigenvalue Decomposition of Symmetric Matrices https://www.computer.org/csdl/journal/si/2026/05/11409369/2en8gxWsKf6 05/31/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664761 RV-WINO: A RISC-V Neural Network Accelerator Based on Winograd Algorithm Fabricated in 55-nm CMOS Process https://www.computer.org/csdl/journal/si/2026/05/11410510/2eoNdZwh5m0 05/31/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3661565 A 45.2-<italic>μ</italic>W Real-Time ASL Gesture Recognition System With Hierarchical Self-Similar Binary Neural Network for Smart Edge Devices https://www.computer.org/csdl/journal/si/2026/05/11413955/2eqrU9lR3c4 05/31/2026 11:07 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3662773 Adaptive Test for Mixed-Signal Chips Based on Information Gain and Backpropagation Neural Network https://www.computer.org/csdl/journal/si/2026/05/11415710/2es6SHpOV44 06/01/2026 8:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3665483 Zero-Instruction-Storage-Overhead Fault-Tolerant Microarchitecture Based on ISA Redundancy and Address-Correlated Hsiao Code https://www.computer.org/csdl/journal/si/2026/05/11419648/2eyKHDcZCrC 05/31/2026 11:12 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3666389 A Hybrid LUT-CORDIC Architecture for High-Performance Rectangular-to-Polar Conversion https://www.computer.org/csdl/journal/si/2026/05/11421048/2eApoMSzyb6 05/31/2026 11:06 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3664080 Highly Efficient Module Design for General Multivariate Nonlinear Functions Using Stochastic Computing https://www.computer.org/csdl/journal/si/2026/05/11421053/2eAppFC24co 05/31/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3662674 Efficient 3-D Convolutional Neural Network Model and VLSI Architecture for Low-Latency and Low-Complexity Processing https://www.computer.org/csdl/journal/si/2026/05/11421076/2eAppM6xgDS 05/31/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3667699 A 28-nm 9-kb SRAM Computing-in-Memory Macro With Segmented Charge Sharing for Multimode MAC Operations https://www.computer.org/csdl/journal/si/2026/05/11421078/2eAppl2XVUA 05/31/2026 11:09 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3668021 MCRA: Multicolumn Residue Accumulation Analog Compute-in-Memory Architecture With Time-Domain M-Input ΣΔ ADC https://www.computer.org/csdl/journal/si/2026/05/11421079/2eAppyR48da 05/31/2026 11:10 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3665471 A 252.8-GOPS and 10.1-TOPS/W Split DP-8T SRAM-Based Analog CIM Macro for 9-bit Signed MAC Operations With High Signal Margin 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https://www.computer.org/csdl/journal/si/2026/05/11538107/2gT4Xeat3Gg 05/31/2026 11:11 pm PST http://doi.ieeecomputersociety.org/10.1109/TVLSI.2026.3679223 30